Simpress: a Simulator Generation Environment for System-on-chip Exploration

of the Thesis SIMPRESS: A Simulator Generation Environment for System-on-Chip Exploration by Asheesh Khare Master of Science in Information and Computer Science University of California, Irvine, 1999 Professor Nikil D. Dutt, Chair Designing Systems-On-Chip (SOC) involves designing embedded applications using customizable embedded processor cores, novel on-chip/o -chip memory hierarchies and highly customizable blocks. Customizable processor cores and other customizable parts imply that the accompanying tool-kit (compiler, simulator, debugger etc.) be easily customizable too. A customizable tool-kit generation approach produces high quality tools from an architecture speci cation. Customizable tool-kits also enable early Design space exploration, improved time-tomarket. In this work we describe SIMPRESS, an environment for generation of simulators for processor-memory architectures. It forms the core component of V{SAT (Visual Speci cation and Analysis Tool), a tool for performing design space exploration of System-On-Chip (SOC) architectures. The other component of V{SAT is a processor-architecture speci cation language, EXPRESSION. In addition to providing early design space exploration in the V{SAT environment, the structural, Cycle-accurate simulators generated from SIMPRESS can be used viii for detailed design of SOC architectures, for application development through code analysis and for testing and evaluating retargetable compilers. Unlike other approaches, SIMPRESS can be used to generate processor simulators for diverse classes of processors such as RISC, VLIW, superscalar etc. We give a detailed description of SIMPRESS and an overview of the V{SAT system (including EXPRESSION, and a GUI for evaluation/analysis) within which it can be integrated. We also present a design space exploration scenario using an example DLX architecture,demonstrating the usefulness of SIMPRESS in exploration for an embedded SOC codesign ow by specifying and evaluating several modi cations to the pipeline structure of the processor. We have used SIMPRESS to model simulators for the DLX, C62X and an almost true size version of the R10000 processors, demonstrating its use in modeling a variety of processor classes. ix CHAPTER